View K4T51163QI-HIE70_7948664.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.0 august 2009 k4t51163qi 1 of 42 industrial ddr2 sdram * samsung electronics reserves the right to chan ge products or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or other- wise, to any intellectual property rights in samsung products or technol- ogy. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sa msung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, me dical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmen tal procurement to which special terms or provisions may apply. 512mb i-die ddr2 sdram specification 84fbga with lead-free and halogen-free (rohs compliant) industrial temp. -40 to 95 c
rev. 1.0 august 2009 k4t51163qi 2 of 42 industrial ddr2 sdram revision history revision month year history 1.0 august 2009 - initial release
rev. 1.0 august 2009 k4t51163qi 3 of 42 industrial ddr2 sdram 1.0 ordering information ....... ................. ................ ................ ................. ................ ............. ............. 4 2.0 key features ......... ................ ................ .............. .............. .............. ............... ............ ........... ....... 4 3.0 package pinout/mechanical dimens ion & addressing ........... .............. .............. ............ ......... 5 3.1 x16 package pinout (top view) : 84ball fbga package .............. .............. .............. .............. ............ 5 3.2 fbga package dimension (x16) ................ ................ .............. .............. .............. .............. ............ 6 4.0 input/output functional description ................ .............. .............. ............... .............. .............. .. 7 5.0 ddr3 sdram addressing .. ................. ................. ................ ................. ................ ................ ..... 8 6.0 absolute maximum ratings ................. ................. ................ ................. ................ ............... ...... 9 7.0 ac & dc operation conditions .... ................. ................ ................ ............... .............. ............ .... 9 7.1 recommended dc operating conditions (sstl - 1.8) ................ .............. .............. .............. ............ 9 7.2 operating temperature condition ............... ................ ................. ................ ................. .............. 10 7.3 input dc logic level ................. ................ ................ ................. ................ ................. .............. 10 7.4 input ac logic level ................. ................ ................ ................. ................ ................. .............. 10 7.5 ac input test conditions ............... ................. ................ ................ ................. .............. ............ 10 7.6 differential input ac logic level ................ .............. .............. .............. .............. .............. ............ 11 7.7 differential ac output parameters ............... ................ ................. ................ ................. .............. 11 8.0 odt dc electrical characte ristics ................. ................ .............. .............. .............. .............. ... 11 9.0 ocd default characteristics ...... ................ ................ .............. ............... .............. .............. ....... 12 10.0 idd specification parame ters and test conditions .. ................ ................. .............. ............ 13 11.0 ddr2 sdram idd spec ..... ................ ................. ................ ................. ................ ............... .... 15 12.0 input/output capacitance .. ............... ................ ................. ................ ................. .............. ....... 16 13.0 electrical characteristics & ac timing for ddr2-800/667 ............ .............. .............. .......... 16 13.1 refresh parameters by device density ................ ................. .............. .............. .............. ............ 16 13.2 speed bins and cl, trcd, trp, trc and tras for corresponding bin ................ ................ ............ 16 13.3 timing parameters by speed grade ................ ................ ................ ................. .............. ............ 17 14.0 general notes, which may apply fo r all ac parameters ................. .............. .............. .......... 19 15.0 specific notes for dedicated ac pa rameters ........... ................ ................. ................ ............ 21 table contents
rev. 1.0 august 2009 k4t51163qi 4 of 42 industrial ddr2 sdram 1.0 ordering information note : 1. speed bin is in order of cl-trcd-trp 2. ?h? of part number(12th digit) stands for lead-free, halogen-free, and rohs compliant products 3. ?i? of part number(13th digit) stand for industrial temp./normal power products 4. ?p? of part number(13th digit) stand for industrial temp./low power products 5. ?d? of part number(13th digit) stand for industrial temp./super low power products 2.0 key features org. ddr2-800 5-5-5 ddr2-800 6-6-6 ddr2-667 5-5-5 package 32mx16 k4t51163qi-hie7 k4t51163qi-hif7 k4t51163qi-hie6 84 fbga k4t51163qi-hpe7 k4t51163qi-hpf7 k4t51163qi-hpe6 k4t51163qi-hde7 - k4t51163qe-hde6 speed ddr2-800 5-5-5 ddr2-800 6-6-6 ddr2-667 5-5-5 units cas latency 5 6 5 tck trcd(min) 12.5 15 15 ns trp(min) 12.5 15 15 ns trc(min) 57.5 60 60 ns ? jedec standard 1.8v 0.1v power supply ? vddq = 1.8v 0.1v ? 333mhz f ck for 667mb/sec/pin, 400mhz f ck for 800mb/sec/ pin ?4 banks ?posted cas ? programmable cas latency: 3, 4, 5 ? programmable additive latency: 0, 1 , 2 , 3 and 4 ? write latency(wl) = read latency(rl) -1 ? burst length: 4 , 8(interleave/nibble sequential) ? programmable sequential / interleave burst mode ? bi-directional differential data-strobe (single-ended data- strobe is an optional feature) ? off-chip driver(ocd) impedance adjustment ? on die termination ? special function support -pasr(partial array self refresh) -50ohm odt -support industrial temp .(case temp. -40 to 95 c) ? average refresh period 7.8us at -40 c < t case < 95 c ? all of lead-free products are compliant for rohs the 512mb ddr2 sdram is organized as a 8mbit x 16 i/os x 4 banks device. this synchronous device achieves high speed dou- ble-data-rate transfer rates of up to 800mb/sec/pin (ddr2-800) for general applications. the chip is designed to comply with the following key ddr2 sdram features such as posted cas with additive latency, write latency = read latency -1, off-chip driver(ocd) impedance adjustment and on die termination. all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. inputs are latched at the crosspoint of differenti al clocks (ck rising and ck falling). all i/os are synchronized with a pair of bidirectional strobes (dqs and dqs ) in a source synchronous fashion. the address bus is used to convey row, column, and bank address information in a ras / cas multiplexing style. the 512mb ddr2 device operates with a single 1.8v 0.1v power supply and 1.8v 0.1v v ddq . the 512mb ddr2 device is available in 84ball fbgas(x16). note: the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of oper- ation. note : this data sheet is an abstract of full ddr2 specificat ion and does not cover the common features which are described in ?samsung?s ddr2 sdram device operation & timing diagram?
rev. 1.0 august 2009 k4t51163qi 5 of 42 industrial ddr2 sdram 3.0 package pinout/mechani cal dimension & addressing 3.1 x16 package pinout (top view) : 84ball fbga package a b c d e f g h j k l vdd nc vss dq6 vssq ldm vddq vddq vddq vssq vssq ldqs ldqs dq7 dq0 vddq dq2 vssq dq5 vssdl vdd ck ras ck cas cs a2 a6 a4 a11 a8 nc nc nc a12 a9 a7 a5 a0 vdd a10/ap vss vddq vssq dq1 dq3 dq4 vddl a1 a3 ba1 vref vss cke we ba0 vdd vss vdd nc vss dq14 vssq udm vddq vddq vssq dq9 dq11 dq12 vddq vddq vssq vssq udqs udqs dq15 udq0 vddq dq10 vssq dq13 nc odt m n p r note : 1. vddl and vssdl are power and ground for the dll. 2. in case of only 8 dqs out of 16 dqs are used, ldqs, ldqsb and dq0~7 must be used. + + + + + + + + + + + 123456789 a b c d e f g h j k l + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + m n p r + + + + + + : populated ball + : depopulated ball top view ball locations (x16) (see the balls through the package) 123 789
rev. 1.0 august 2009 k4t51163qi 6 of 42 industrial ddr2 sdram 3.2 fbga package dimension (x16) b c d e f g h j k l a 7.50 0.10 6.40 0.80 1.60 # a1 index mark 0.80 x 8 = 1 2 3 4 5 6 7 8 9 3.20 12.50 0.10 0.80 0.80 0.80 11.20 x 14 = 5.60 (0.95) (1.90) 84- ? 0.45 solder ball 0.2 m ab (post reflow 0.50 0.05) (datum a) (datum b) a b molding area 7.50 0.10 0.10max 0.35 0.05 1.10 0.10 bottom top 12.50 0.10 m n p r #a1 units : millimeters
rev. 1.0 august 2009 k4t51163qi 7 of 42 industrial ddr2 sdram 4.0 input/output functional description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck (both directions of crossing). cke input clock enable: cke high activates, and cke low deactivates, inte rnal clock signals and device input buffers and out- put drivers. taking cke low provides precharge power-down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is synchronous for power down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit. after v ref has become stable during the power on and initialization sequence, it must be maintained for proper operation of the cke receiver. for proper self-refresh entry and exit, v ref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power-down. i nput buffers, excluding cke, are disabled during self refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external rank selection on sys- tems with multiple ranks. cs is considered part of the command code. odt input on die termination: odt (registered high) enables termi nation resistance internal to the ddr2 sdram. for x16 configuration odt is appl ied to each dq, udqs/udqs , ldqs/ldqs , udm, and ldm signal. the odt pin will be ignored if the extended mode register (emr s(1)) is programmed to disable odt. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coinci- dent with that input data during a write access. dm is sa mpled on both edges of dqs. although dm pins are input only, the dm loading matches the dq and dqs loading. ba0 - ba1 input bank address inputs: ba0 - ba1 define to which bank an active, read, write or precharge command is being applied. bank address also determines if the mode register or extended mode regi ster is to be accessed during a mrs or emrs cycle. a0 - a13 input address inputs: provided the row address for active commands and the column address and auto precharge bit for read/write commands to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge appli es to one bank (a10 low) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba0, ba1. the address inputs also provide the op-code dur- ing mode register set commands. dq input/out- put data input/ output: bi-directional data bus. dqs, (dqs ) (ldqs), (ldqs ) (udqs), (udqs ) input/out- put data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. for the x16, ldqs corresponds to the data on dq0-dq7; udqs corresponds to the data on dq8-dq15. the data strobes dqs, ldqs and udqs may be used in single ended mode or paired with optional complementary signals dqs , ldqs and udqs to provide differential pair signaling to the system during both reads and writes. an emrs(1) control bit enables or disables all comp lementary data strobe signals. in this data sheet, "differential dqs signals" refers to any of the following with a10 = 0 of emrs(1) x16 ldqs/ldqs and udqs/udqs "single-ended dqs signals" refers to any of the following with a10 = 1 of emrs(1) x16 ldqs and udqs nc no connect: no internal electrical connection is present. v dd /v ddq supply power supply: 1.8v +/- 0.1v, dq power supply: 1.8v +/- 0.1v v ss /v ssq supply ground , dq ground v ddl supply dll power supply: 1.8v +/- 0.1v v ssdl supply dll ground v ref supply reference voltage
rev. 1.0 august 2009 k4t51163qi 8 of 42 industrial ddr2 sdram 5.0 ddr3 sdram addressing 512mb * reference information: the following tables are address mapping information for other densities. 256mb 1gb 2gb 4gb configuration 128mb x4 64mb x 8 32mb x16 # of banks 4 4 4 bank address ba0,ba1 ba0,ba1 ba0,ba1 auto precharge a10/ap a10/ap a10/ap row address a0 ~ a13 a0 ~ a13 a0 ~ a12 column address a0 ~ a9,a11 a0 ~ a9 a0 ~ a9 configuration 64mb x4 32mb x 8 16mb x16 # of banks 4 4 4 bank address ba0,ba1 ba0,ba1 ba0,ba1 auto precharge a10/ap a10/ap a10/ap row address a0 ~ a12 a0 ~ a12 a0 ~ a12 column address a0 ~ a9,a11 a0 ~ a9 a0 ~ a8 configuration 256mb x4 128mb x 8 64mb x16 # of banks 8 8 8 bank address ba0 ~ ba2 ba0 ~ ba2 ba0 ~ ba2 auto precharge a10/ap a10/ap a10/ap row address a0 ~ a13 a0 ~ a13 a0 ~ a12 column address a0 ~ a9,a11 a0 ~ a9 a0 ~ a9 configuration 512mb x4 256mb x 8 128mb x16 # of banks 8 8 8 bank address ba0 ~ ba2 ba0 ~ ba2 ba0 ~ ba2 auto precharge a10/ap a10/ap a10/ap row address a0 ~ a14 a0 ~ a14 a0 ~ a13 column address a0 ~ a9,a11 a0 ~ a9 a0 ~ a9 configuration 1 gb x4 512mb x 8 256mb x16 # of banks 8 8 8 bank address ba0 ~ ba2 ba0 ~ ba2 ba0 ~ ba2 auto precharge a10/ap a10/ap a10/ap row address a0 - a15 a0 - a15 a0 - a14 column address/page size a0 - a9,a11 a0 - a9 a0 - a9
rev. 1.0 august 2009 k4t51163qi 9 of 42 industrial ddr2 sdram 6.0 absolute maximum ratings note : 1. stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those i ndicated in the operational sections of this s pecification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. 3. v dd and v ddq must be within 300mv of each other at all times; and v ref must be not greater than 0.6 x v ddq . when v dd and v ddq and v ddl are less than 500mv, v ref may be equal to or less than 300mv. 4. voltage on any input or i/o may not exceed voltage on v ddq . 7.0 ac & dc operation conditions 7.1 recommended dc operating conditions (sstl - 1.8) note : there is no specific device v dd supply voltage requirement for sstl-1.8 co mpliance. however under all conditions v ddq must be less than or equal to v dd . 1. the value of v ref may be selected by the user to pr ovide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 2. peak to peak ac noise on v ref may not exceed +/-2% v ref (dc). 3. v tt of transmitting device must track v ref of receiving device. 4. ac parameters are measured with v dd , v ddq and v ddl tied together. symbol parameter rating units notes v dd voltage on v dd pin relative to v ss - 1.0 v ~ 2.3 v v 1 v ddq voltage on v ddq pin relative to v ss - 0.5 v ~ 2.3 v v 1 v ddl voltage on v ddl pin relative to v ss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to v ss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 c 1, 2 symbol parameter rating units notes min. typ. max. v dd supply voltage 1.7 1.8 1.9 v v ddl supply voltage for dll 1.7 1.8 1.9 v 4 v ddq supply voltage for output 1.7 1.8 1.9 v 4 v ref input reference voltage 0.49*v ddq 0.50*v ddq 0.51*v ddq mv 1,2 v tt termination voltage v ref -0.04 v ref v ref +0.04 v 3
rev. 1.0 august 2009 k4t51163qi 10 of 42 industrial ddr2 sdram 7.2 operating temperature condition note : 1. operating temperature is the case surface temperature on the center/top side of the dram. 7.3 input dc logic level 7.4 input ac logic level note : 1. for information related to v peak value, refer to overshoot/undershoot specification in devi ce operation and timing datas heet; maximum peak ampli- tude allowed for overshoot and undershoot. 7.5 ac input test conditions note : 1. input waveform timing is referenced to the input signal crossing through the v ih/il (ac) level applied to the device under test. 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) min for rising edges and the range from v ref to v il (ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. symbol parameter rating units notes t oper operating temperature -40 to 95 c 1, 2 symbol parameter min. max. units notes v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v symbol parameter ddr2-667, ddr2-800 units min. max. v ih (ac) ac input logic high v ref + 0.200 v ddq + v peak v v il (ac) ac input logic low v ssq - v peak v ref - 0.200 v symbol condition value units notes v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss < ac input test signal waveform > v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr
rev. 1.0 august 2009 k4t51163qi 11 of 42 industrial ddr2 sdram 7.6 differential input ac logic level note : 1. v id (ac) specifies the input differential voltage |v tr -v cp | required for switching, where v tr is the true input signal (such as ck, dqs, ldqs or udqs) and v cp is the complementary input signal (such as ck , dqs , ldqs or udqs ). the minimum value is equal to v ih (ac) - v il (ac). 2. the typical value of v ix (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ix (ac) is expected to track variations in v ddq . v ix (ac) indicates the voltage at which differential input signals must cross. 3. for information related to v peak value, refer to overshoot/undershoot specification in devi ce operation and timing datas heet; maximum peak ampli- tude allowed for overshoot and undershoot. 7.7 differential ac output parameters note : 1. the typical value of v ox (ac) is expected to be about 0.5 * v ddq of the transmitting device and v ox (ac) is expected to track variations in v ddq . v ox (ac) indicates the voltage at which differential output signals must cross. 8.0 odt dc electrical characteristics note : 1. test condition for rtt measurements measurement definition for rtt(eff) : apply v ih (ac) and v il (ac) to test pin separately, then measure current i(v ih (ac)) and i( v il (ac)) respectively. v ih (ac), v il (ac), and v ddq values defined in sstl_18 measurement definition for vm: measure voltage (v m ) at test pin (midpoint) with no load. symbol parameter min. max. units notes v id(ac) ac differential input voltage 0.5 v ddq v1 v ix(ac) ac differential cross point voltage 0.5 * v ddq - 0.175 0.5 * v ddq + 0.175 v 2 symbol parameter min. max. units note v ox (ac) ac differential cross point voltage 0.5 * v ddq - 0.125 0.5 * v ddq + 0.125 v 1 parameter/condition symbol min nom max units notes rtt effective impedance value for emrs(a6,a2)=0,1; 75 ohm rtt1(eff) 60 75 90 ohm 1 rtt effective impedance value for emrs(a6,a2)=1,0; 150 ohm rtt2(eff) 120 150 180 ohm 1 rtt effective impedance value for emrs(a6,a2)=1,1; 50 ohm rtt3(eff) 40 50 60 ohm 1 deviation of vm with respect to v ddq /2 delta vm - 6 + 6 % 1 v ddq crossing point v ssq v tr v cp v id v ix or v ox < differential signal levels > rtt(eff) = v ih (ac) - v il (ac) i( v ih (ac) ) - i( v il (ac) ) delta v m = 2 x vm v ddq x 100% - 1
rev. 1.0 august 2009 k4t51163qi 12 of 42 industrial ddr2 sdram 9.0 ocd default characteristics note : 1. absolute specifications (-40c t case +95c; v dd = +1.8v 0.1v, v ddq = +1.8v 0.1v) 2. impedance measurement condition for output source dc current: v ddq = 1.7v; v out = 1420mv; (v out -v ddq )/ioh must be less than 23.4 ohms for values of v out between v ddq and v ddq - 280mv. impedance measurement conditi on for output sink dc current: v ddq = 1.7v; v out = 280mv; v out /iol must be less than 23.4 ohms for values of v out between 0v and 280mv. 3. mismatch is absolute value between pull-up and pull- dn, both are measured at same temperature and voltage. 4. slew rate measured from v il (ac) to v ih (ac). 5. the absolute value of the slew rate as measured from dc to dc is equal to or greater than the slew rate as measured from ac to ac. this is guaran- teed by design and characterization. 6. this represents the step size when the ocd is near 18 ohms at nominal conditions across all process and represents only the dram uncertainty. output slew rate load : 7. dram output slew rate specification applie s to 667mb/sec/pin and 800mb/sec/pin speed bins. 8. timing skew due to dram output slew rate mis-match between dqs / dqs and associated dqs is included in tdqsq and tqhs specification. description parameter min nom max unit notes output impedance 18ohm at nominal condition see full strength default driver characteristics on device operation specification ohms 1,2 output impedance step size for ocd calibration 0 1.5 ohms 6 pull-up and pull-down mismatch 0 4 ohms 1,2,3 output slew rate sout 1.5 5 v/ns 1,4,5,6,7,8 25 ohms vtt output (vout) reference point
rev. 1.0 august 2009 k4t51163qi 13 of 42 industrial ddr2 sdram 10.0 idd specificatio n parameters and test conditions (idd values are for full operating range of voltage and temperature, notes 1-5) symbol proposed conditions units notes idd0 operating one bank active-precharge current ; t ck = t ck(idd), t rc = t rc(idd), t ras = t rasmin(idd); cke is high, cs\ is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t rc = t rc (idd), t ras = t rasmin(idd), t rcd = t rcd(idd); cke is high, cs\ is high between valid co mmands; address bus inputs are switching; data pat- tern is same as idd4w ma idd2p precharge power-down current ; all banks idle; t ck = t ck(idd); cke is low; other control and addres s bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ; all banks idle; t ck = t ck(idd); cke is high, cs\ is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; t ck = t ck(idd); cke is high, cs\ is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; t ck = t ck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0ma ma slow pdn exit mrs(12) = 1ma ma idd3n active standby current ; all banks open; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t rasmax(idd), t rp = t rp(idd); cke is high, cs\ is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; t ck = t ck(idd), t ras = t ras- max(idd), t rp = t rp(idd); cke is high, cs\ is high between va lid commands; address bus inputs are switch- ing; data pattern is same as idd4w ma idd5b burst auto refresh current ; t ck = t ck(idd); refresh command at every t rfc(idd) interval; cke is high, cs\ is high between valid com- mands; other control and address bus inputs ar e switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck\ at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal ma low power ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl(idd), al = t rcd(idd)-1* t ck(idd); t ck = t ck(idd), t rc = t rc(idd), t rrd = t rrd(idd), t faw = t faw(idd), t rcd = 1* t ck(idd); cke is high, cs\ is high between valid commands; address bus inputs are stable during deselects; data pattern is same as idd4r; refer to the fol- lowing page for detailed timing conditions ma
rev. 1.0 august 2009 k4t51163qi 14 of 42 industrial ddr2 sdram note : 1. idd specifications are tested afte r the device is properly initialized 2. input slew rate is specified by ac parametric test condition 3. idd parameters are specified with odt disabled. 4. data bus consists of dq, dm, dqs, dqs , rdqs, rdqs , ldqs, ldqs , udqs, and udqs . idd values must be met with all combinations of emrs bits 10 and 11. 5. definitions for idd low is defined as v in v il (ac) max high is defined as v in v ih (ac) min stable is defined as inputs stable at a high or low level floating is defined as inputs at v ref = v ddq /2 switching is defined as: inputs changing betw een high and low every other clock cycle (once per two clocks) for address and control signals, and inputs changing between high and lo w every other data transfer (once pe r clock) for dq signals not includi ng masks or strobes. for purposes of idd testing, t he following parameters are utilized detailed idd7 the detailed timings are shown below for idd7. legend: a = active; ra = read with autoprecharge; d = deselect idd7: operating current: all bank interleave read operation all banks are being interleaved at minimum trc(idd) without violat ing trrd(idd) and tfaw(idd) using a burst length of 4. contro l and address bus inputs are stable during deselects. iout = 0ma timing patterns for 4 bank devices x4/ x8/ x16 -ddr2-667 5/5/5 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d -ddr2-800 6/6/6 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d d -ddr2-800 5/5/5 a0 ra0 d d a1 ra1 d d a2 ra2 d d a3 ra3 d d d d d d d d d ddr2-800 ddr2-800 ddr2-667 units parameter 5-5-5 6-6-6 5-5-5 cl(idd) 5 6 5 tck trcd(idd) 12.5 15 15 ns trc(idd) 57.5 60 60 ns trrd(idd)-x4/x8 7.5 7.5 7.5 ns trrd(idd)-x16 10 10 10 ns tck(idd) 2.5 2.5 3 ns trasmin(idd) 45 45 45 ns trp(idd) 12.5 15 15 ns trfc(idd) 105 105 105 ns
rev. 1.0 august 2009 k4t51163qi 15 of 42 industrial ddr2 sdram 11.0 ddr2 sdram idd spec symbol 32mx16 (k4t51163qi) unit notes 800@cl=5 800@cl=6 667@cl=5 ie7 pe7 de7 if7 pf7 ie6 pe6 de6 idd0 67 67 65 ma idd1 80 80 75 ma idd2p85585855ma idd2q252525ma idd2n303030ma idd3p-f282828ma idd3p-s101010ma idd3n404038ma idd4w959585ma idd4r 130 130 115 ma idd5 90 90 90 ma idd6 84384843ma idd7 200 200 185 ma
rev. 1.0 august 2009 k4t51163qi 16 of 42 industrial ddr2 sdram 12.0 input/output capacitance 13.0 electrical characteristics & ac timing for ddr2-800/667 ( -40 c < t oper < 95 c; v ddq = 1.8v + 0.1v; v dd = 1.8v + 0.1v) 13.1 refresh parameters by device density 13.2 speed bins and cl, trcd, trp, trc and tras for corresponding bin parameter symbol ddr2-667 ddr2-800 units min max min max input capacitance, ck and ck cck 1.0 2.0 1.0 2.0 pf input capacitance delta, ck and ck cdck x 0.25 x 0.25 pf input capacitance, all other input-only pins ci 1.0 2.0 1.0 1.75 pf input capacitance delta, all other input-only pins cdi x 0.25 x 0.25 pf input/output capacitance, dq, dm, dqs, dqs cio 2.5 3.5 2.5 3.5 pf input/output capacitance delta, dq, dm, dqs, dqs cdio x 0.5 x 0.5 pf parameter symbol 256mb 512mb 1gb 2gb 4gb units refresh to active/refresh command time trfc 75 105 127.5 195 327.5 ns average periodic refresh interval trefi -40 c t case 95 c 7.8 7.8 7.8 7.8 7.8 s speed ddr2-800(e7) ddr2-800(f7) ddr2-667(e6) units bin (cl - trcd - trp) 5-5-5 6-6-6 5 - 5 - 5 parameter min max min max min max tck, cl=3 5 8 - - 5 8 ns tck, cl=4 3.75 8 3.75 8 3.75 8 ns tck, cl=5 2.5 8 3 8 3 8 ns tck, cl=6 - - 2.5 8 - - ns trcd 12.5 - 15 - 15 - ns trp 12.5 - 15 - 15 - ns trc 57.5 - 60 - 60 - ns tras 45 70000 45 70000 45 70000 ns
rev. 1.0 august 2009 k4t51163qi 17 of 42 industrial ddr2 sdram 13.3 timing parameters by speed grade (for information related to the entries in this table, refer to both the general notes and the specific notes following this ta ble.) parameter symbol ddr2-800 ddr2-667 units notes min max min max dq output access time from ck/ck tac -400 400 -450 450 ps 40 dqs output access time from ck/ck tdqsck -350 350 -400 400 ps 40 average clock high pulse width tch(avg) 0.48 0.52 0.48 0.52 tck(avg) 35,36 average clock low pulse width tcl(avg) 0.48 0.52 0.48 0.52 tck(avg) 35,36 ck half pulse period thp min(tcl(abs), tch(abs)) x min(tcl(abs), tch(abs)) x ps 37 average clock period tck(avg) 2500 8000 3000 8000 ps 35,36 dq and dm input hold time tdh(base) 125 x 175 x ps 6,7,8,21 ,28,31 dq and dm input setup time tds(base) 50 x 100 x ps 6,7,8,20 ,28,31 control & address input pulse width for each input tipw 0.6 x 0.6 x tck(avg) dq and dm input pulse width for each input tdipw 0.35 x 0.35 x tck(avg) data-out high-impedance time from ck/ck thz x tac(max) x tac(max) ps 18,40 dqs/dqs low-impedance time from ck/ck tlz(dqs) tac(min) tac(max) tac(min) tac(max) ps 18,40 dq low-impedance time from ck/ck tlz(dq) 2* tac(min) tac(max) 2* tac(min) tac(max) ps 18,40 dqs-dq skew for dqs and associated dq signals tdqsq x 200 x 240 ps 13 dq hold skew factor tqhs x 300 x 340 ps 38 dq/dqs output hold time from dqs tqh thp - tqhs x thp - tqhs x ps 39 dqs latching rising transitions to associated clock edges tdqss - 0.25 0.25 -0.25 0.25 tck(avg) 30 dqs input high pulse width tdqsh 0.35 x 0.35 x tck(avg) dqs input low pulse width tdqsl 0.35 x 0.35 x tck(avg) dqs falling edge to ck setup time tdss 0.2 x 0.2 x tck(avg) 30 dqs falling edge hold time from ck tdsh 0.2 x 0.2 x tck(avg) 30 mode register set command cycle time tmrd 2 x 2 x nck mrs command to odt update delay tmod 0 12 0 12 ns 32 write postamble twpst 0.4 0.6 0.4 0.6 tck(avg) 10 write preamble twpre 0.35 x 0.35 x tck(avg) address and control input hold time tih(base) 250 x 275 x ps 5,7,9,23 ,29 address and control input setup time tis(base) 175 x 200 x ps 5,7,9,22 ,29 read preamble trpre 0.9 1.1 0.9 1.1 tck(avg) 19,41 read postamble trpst 0.4 0.6 0.4 0.6 tck(avg) 19,42 activate to activate command period for 1kb page size products trrd 7.5 x 7.5 x ns 4,32 activate to activate command period for 2kb page size products trrd 10 x 10 x ns 4,32
rev. 1.0 august 2009 k4t51163qi 18 of 42 industrial ddr2 sdram parameter symbol ddr2-800 ddr2-667 units notes min max min max four activate window for 1kb page size products tfaw 35 x 37.5 x ns 32 four activate window for 2kb page size products tfaw 45 x 50 x ns 32 cas to cas command delay tccd 2 x 2 x nck write recovery time twr 15 x 15 x ns 32 auto precharge write recovery + precharge time tdal wr + tnrp x wr + tnrp x nck 33 internal write to read command delay twtr 7.5 x7.5 x ns 24,32 internal read to precharge command delay trtp 7.5 x7.5 x ns 3,32 exit self refresh to a non-read command txsnr trfc + 10 x trfc + 10 x ns 32 exit self refresh to a read command txsrd 200 x200 x nck exit precharge power down to any command txp 2 x 2 x nck exit active power down to read command txard 2 x 2 x nck 1 exit active power down to read command (slow exit, lower power) txards 8 - al x 7 - al x nck 1,2 cke minimum pulse width (high and low pulse width) tcke 3 x 3 x nck 27 odt turn-on delay taond 2 2 2 2 nck 16 odt turn-on taon tac(min) tac(max)+0.7 tac(min) tac(max)+0.7 ns 6,16,40 odt turn-on (power-down mode) taonpd tac(min)+2 2*tck(avg) +tac(max)+1 tac(min)+2 2*tck(avg) +tac(max)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 nck 17,45 odt turn-off taof tac(min) tac(max)+0.6 tac(min) tac(max)+0.6 ns 17,43,4 5 odt turn-off (power-down mode) taofpd tac(min)+2 2.5*tck(avg)+tac (max)+1 tac(min)+2 2.5*tck(avg)+tac (max)+1 ns odt to power down entry latency tanpd 3 x3 x nck odt power down exit latency taxpd 8 x8 x nck ocd drive mode output delay toit 0 12 0 12 ns 32 minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck(avg) +tih x tis+tck(avg) +tih xns15
rev. 1.0 august 2009 k4t51163qi 19 of 42 industrial ddr2 sdram 14.0 general notes, which may apply for all ac parameters 1. ddr2 sdram ac timing reference load figure 1 represents the timing reference l oad used in defining the relevant timing parameters of the part. it is not intended t o be either a precise repre sentation of the typical system environment or a depiction of the actual load presented by a production tester. system designer s will use ibis or other sim- ulation tools to correlate the timing refe rence load to a system environment. manufactu rers will correlate to their production test conditions (generally a coaxial transmission line termi nated at the tester electronics). the output timing reference voltage level fo r single ended signals is the cros spoint with vtt. the output timing reference volt age level for differential signals is the crosspoint of the true (e.g. dqs) and the complement (e.g. dqs ) signal. 2. slew rate measurement levels a) output slew rate for falling and rising edges is measur ed between vtt - 250 mv and vtt + 250 mv for single ended signals. fo r differential signals (e.g. dqs - dqs ) output slew rate is measured between dqs - dqs = - 500 mv and dqs - dqs = + 500 mv. output slew rate is guaranteed by design, but is not necessa rily tested on each device. b) input slew rate for single ended signals is measured from vref (dc) to vih(ac),min for rising edges and from vref(dc) to vil( ac),max for falling edges. for differential signals (e.g. ck - ck ) slew rate for rising edges is measured from ck - ck = - 250 mv to ck - ck = + 500 mv (+ 250 mv to - 500 mv for falling edges). c) vid is the magnitude of the difference between the input voltage on ck and the input voltage on ck , or between dqs and dqs for differential strobe. 3. ddr2 sdram output slew rate test load output slew rate is characterized under the test conditions as shown in figure 2. vddq dut dq dqs dqs output v tt = v ddq /2 25 ? timing reference point figure 1 - ac timing reference load rdqs rdqs vddq dut dq dqs, dqs rdqs, rdqs output v tt = v ddq /2 25 ? test point figure 2 - slew rate test load
rev. 1.0 august 2009 k4t51163qi 20 of 42 industrial ddr2 sdram 4. differential data strobe ddr2 sdram pin timings are specified for either single ended mode or differential mode depending on the setting of the emrs "en able dqs" mode bit; timing advantages of differential mode are realized in system des ign. the method by which the ddr 2 sdram pin timings are measur ed is mode depen- dent. in single ended mode, timing relationships are measured relati ve to the rising or falling edges of dqs crossing at vref. in differential mode, these timing relationships are measured relative to the crosspoint of dqs and its complement, dqs . this distinction in timing me thods is guaranteed by design and characterization. note that when differential data strobe mode is disabled via the emrs, the complementary pin, dqs , must be tied externally to vss through a 20 ? to 10 k ? resistor to insure proper operation. 5. ac timings are for linear signal transitions. see specific notes on de rating for other signal transitions. 6. all voltages are referenced to vss. 7. these parameters guarantee device behavior, but they are not necessarily tested on each device. they may be guaranteed by devic e design or tester correlation. 8. tests for ac timing, idd, and electrical (ac and dc) characte ristics, may be conducted at nomi nal reference/supply voltage lev els, but the related specifications and device operation are guarant eed for the full voltage range specified. t ds t ds t dh t wpre t wpst t dqsh t dqsl dqs dqs d dmin dqs/ dq dm t dh figure 3 - data input (write) timing dmin dmin dmin d d d dqs v il (ac) v ih (ac) v il (ac) v ih (ac) v il (dc) v ih (dc) v il (dc) v ih (dc) t ch t cl ck ck ck/ck dqs/dqs dq dqs dqs t rpst q t rpre t dqsqmax t qh t qh t dqsqmax q qq figure 4 - data output (read) timing
rev. 1.0 august 2009 k4t51163qi 21 of 42 industrial ddr2 sdram 15.0 specific notes for dedicated ac parameters 1. user can choose which active power down ex it timing to use via mrs (bit 12). txard is expected to be used for fast active powe r down exit timing. txards is expected to be used for sl ow active power down exit timing. 2. al = additive latency. 3. this is a minimum requirement. minimum read to precharge timing is al + bl / 2 prov ided that the trtp and tras(min) have been s atisfied. 4. a minimum of two clocks (2 x tck or 2 x nck) is required irrespective of operating frequency. 5. timings are specified with command/addr ess input slew rate of 1.0 v/ns. 6. timings are specified with dqs, dm, and dqs?s (dqs/rdq s in single ended mode) input slew rate of 1.0v/ns. 7. timings are specified with ck/ck differential slew rate of 2.0 v/ns. timings are guaranteed for dqs signals with a differential slew rate of 2.0 v/ns in differential strobe mode and a slew rate of 1.0 v/ns in single ended mode. 8. data setup and hold time derating. [ table 1 ] ddr2-400/533 tds/tdh derating with differential data strobe [ table 2 ] ddr2-667/800 tds/tdh derating with differential data strobe ? tds, ? tdh derating values of ddr2-400, ddr2-533 (all units in ?ps?, the note applies to entire table) dqs,dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns 0.8v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh dq siew rate v/ns 2.0 125 45 125 45 125 45 - - - - - - - - - - - - 1.58321832183219533 - - - - - - - - - - 1.000000012122424-------- 0.9 - - -11 -14 -11 -14 1 -2 13 10 25 22 - - - - - - 0.8 - - - - -25 -31 -13 -19 -1 -7 11 5 23 17 - - - - 0.7-------31-42-19-30-7-185-6176-- 0.6 - - - - - - - - -43 -59 -31 -47 -19 -35 -7 -23 5 -11 0.5 - - - - - - - - - - -74 -89 -62 -77 -50 -65 -38 -53 0.4 - - - - - - - - - - - - -127 -140 -115 -128 -103 -116 ? tds, ? tdh derating values for ddr2-667, ddr2-800 (all units in ?ps?, the note applies to entire table) dqs,dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns 0.8v/ns ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh ? tds ? tdh dq slew rate v/ns 2.0100451004510045------------ 1.56721672167217933---------- 1.000000012122424-------- 0.9---5-14-5-147-219103122------ 0.8-----13-31-1-1911-72353517---- 0.7-------10-422-3014-1826-6386-- 0.6---------10-592-4714-3526-2338-11 0.5-----------24-89-12-770-6512-53 0.4-------------52-140-40-128-28-116
rev. 1.0 august 2009 k4t51163qi 22 of 42 industrial ddr2 sdram [ table 3 ] ddr2-400/533 tds1/tdh1 derating with single ended data strobe for all input signals the total tds (setup time) and tdh (hold ti me) required is calculated by adding the data sheet tds(base) and tdh(base) value to the ? tds and ? tdh derating value respectively. example: tds (total setup time) =tds(base) + ? tds. setup (tds) nominal slew rate for a rising signal is defined as t he slew rate between the last crossing of vref(dc) and the fir st crossing of vih(ac)min. setup (tds) nominal slew rate for a fallin g signal is defined as the slew rate between the last crossing of vref(dc) and the fi rst crossing of vil(ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded ?vre f(dc) to ac region?, use nominal slew ra te for derating value (see figure 5 for differential data strobe and figure 6 for single-ended dat a strobe.) if the actual signal is later than the nomina l slew rate line anywhere between shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is u sed for derating value (see figure 7 for differential data strobe and figure 8 for single-ended data strobe) hold (tdh) nominal slew rate for a rising signal is defined as the slew rate betw een the last crossing of vil(dc)max and the fi rst crossing of vref(dc). hold (tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nomi nal slew rate line between shaded ?dc level to vref(dc) region?, use nominal slew ra te for derating value (see figure 9 for differential data strobe and figure 10 for single- ended data strobe) if the actual signal is earlier than the nomi nal slew rate line anywhere between shaded ?dc to vref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) leve l is used for derating value (see figure 11 for differential data strobe and figure 12 for single-ended data strobe) although for slow slew rates the total setup time might be negat ive (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac). for slew rates in between the values listed in table 1 the derating values may obtai ned by linear interpolation. these values are typically not subj ect to production test. they are ve rified by design and characterization. ? tds1, ? tdh1 derating values for ddr2-400, ddr2-533(all units in ?ps?; the note applies to the entire table) dqs single-ended slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns 0.9 v/ns 0.8 v/ns 0.7 v/ns 0.6 v/ns 0.5 v/ns 0.4 v/ns ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 ? tds 1 ? tdh 1 dq slew rate v/ns 2.018818816714612563------------ 1.514616712512583428143---------- 1.063125428300-21-7-13-------- 0.9 - - 31 69 -11 -14 -13 -13 -18 -27 -29 -45 - - - - - - 0.8 - - - - -25 -31 -27 -30 -32 -44 -43 -62 -60 -86 - - - - 0.7 - - - - - - -45 -53 -50 -67 -61 -85 -78 -109 -108 -152 - - 0.6---------74-96-85-114-102-138-138-181-183-246 0.5-----------128-156-145-180-175-223-226-288 0.4-------------210-243-240-286-291-351
rev. 1.0 august 2009 k4t51163qi 23 of 42 industrial ddr2 sdram v ss tds tdh setup slew rate setup slew rate rising signal falling signal ? tf ? tr v ref(dc) - vil(ac)max ? tf = vih(ac)min - v ref(dc) ? tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate vref to ac region vref to ac region tds tdh tvac dqs dqs figure 5 - illustration of nominal slew rate for tds (differential dqs,dqs )
rev. 1.0 august 2009 k4t51163qi 24 of 42 industrial ddr2 sdram v ss tds tdh setup slew rate setup slew rate rising signal falling signal ? tf ? tr v ref(dc) - vil(ac)max ? tf = vih(ac)min - v ref(dc) ? tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate vref to ac region vref to ac region dqs figure 6 - illustration of nominal slew rate for tds (single-ended dqs) v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss tdh tds note1 note : dqs signal must be monotonic between vil(dc)max and vih(dc)min.
rev. 1.0 august 2009 k4t51163qi 25 of 42 industrial ddr2 sdram v ss setup slew rate setup slew rate rising signal falling signal ? tf ? tr tangent line[v ref(dc) - vil(ac)max] ? tf = tangent line[vih(ac)min - v ref(dc) ] ? tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line tds tdh tds tdh dqs dqs figure 7 - illustration of tangent line for tds (differential dqs, dqs )
rev. 1.0 august 2009 k4t51163qi 26 of 42 industrial ddr2 sdram v ss setup slew rate setup slew rate rising signal falling signal ? tf ? tr tangent line[v ref(dc) - vil(ac)max] ? tf = tangent line[vih(ac)min - v ref(dc) ] ? tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line figure 8 - illustration of tangent line for tds (single-ended dqs) tds tdh dqs v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss tdh tds note1 note : dqs signal must be monotonic between vil(dc)max and vih(dc)min.
rev. 1.0 august 2009 k4t51163qi 27 of 42 industrial ddr2 sdram v ss hold slew rate hold slew rate falling signal rising signal ? tr ? tf v ref(dc) - vil(dc)max ? tr = vih(dc)min - v ref(dc) ? tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region tds tdh tds tdh dqs dqs figure 9 - illustration of nominal slew rate for tdh (differential dqs, dqs )
rev. 1.0 august 2009 k4t51163qi 28 of 42 industrial ddr2 sdram v ss hold slew rate hold slew rate falling signal rising signal ? tr ? tf v ref(dc) - vil(dc)max ? tr = vih(dc)min - v ref(dc) ? tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region figure 10 - illustration of nominal slew rate for tdh (single-ended dqs) tds tdh dqs v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss tdh tds note1 note : dqs signal must be monotoni c between vil(dc)max and vih(dc)min.
rev. 1.0 august 2009 k4t51163qi 29 of 42 industrial ddr2 sdram v ss hold slew rate ? tf ? tr tangent line [ vih(dc)min - v ref(dc) ] ? tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - vil(dc)max ] ? tr = rising signal tds tdh tds tdh dqs dqs figure 11 - illustration of tangent line for tdh (differential dqs, dqs )
rev. 1.0 august 2009 k4t51163qi 30 of 42 industrial ddr2 sdram v ss hold slew rate ? tf ? tr tangent line [ vih(dc)min - v ref(dc) ] ? tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - vil(dc)max ] ? tr = rising signal figure 12 - illustration of tangent line for tdh (single-ended dqs) note : dqs signal must be monotonic between vil(dc)max and vih(dc)min. tds tdh dqs v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max v ss tdh tds note1
rev. 1.0 august 2009 k4t51163qi 31 of 42 industrial ddr2 sdram 9. tis and tih (input setup and hold) derating [ table 4 ] derating values for ddr2-400, ddr2-533 ? tis, ? tih derating values for ddr2-400, ddr2-533 ck, ck differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns units notes ? tis ? tih ? tis ? tih ? tis ? tih command/ address slew rate(v/ns) 4.0 +187 +94 +217 +124 +247 +154 ps 1 3.5 +179 +89 +209 +119 +239 +149 ps 1 3.0 +167 +83 +197 +113 +227 +143 ps 1 2.5 +150 +75 +180 +105 +210 +135 ps 1 2.0 +125 +45 +155 +75 +185 +105 ps 1 1.5 +83 +21 +113 +51 +143 +81 ps 1 1.0 0 0 +30 +30 +60 +60 ps 1 0.9 -11 -14 +19 +16 +49 +46 ps 1 0.8 -25 -31 +5 -1 +35 +29 ps 1 0.7 -43 -54 -13 -24 +17 +6 ps 1 0.6 -67 -83 -37 -53 -7 -23 ps 1 0.5 -110 -125 -80 -95 -50 -65 ps 1 0.4 -175 -188 -145 -158 -115 -128 ps 1 0.3 -285 -292 -255 -262 -225 -232 ps 1 0.25 -350 -375 -320 -345 -290 -315 ps 1 0.2 -525 -500 -495 -470 -465 -440 ps 1 0.15 -800 -708 -770 -678 -740 -648 ps 1 0.1 -1450 -1125 -1420 -1095 -1390 -1065 ps 1
rev. 1.0 august 2009 k4t51163qi 32 of 42 industrial ddr2 sdram [ table 5 ] derating values for ddr2-667, ddr2-800 for all input signals the total tis (setup time) and tih (hold ti me) required is calculated by adding the data sheet tis(base) and tih(base) value to the ? tis and ? tih derating value respectively. example: tis (total setup time) = tis(base) + ? tis setup (tis) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref(dc) and the fir st crossing of vih(ac)min. setup (tis) nominal slew rate for a falli ng signal is defined as the slew rate between the last crossing of vref(dc) and the fi rst crossing of vil(ac)max. if the actual signal is always ear lier than the nominal slew rate line between sha ded ?vref(dc) to ac regi on?, use nominal slew ra te for derating value (see figure 13). if the actual signal is later than the nominal slew rate line anywhere between shaded ?vref(dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see figure 14). hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vil(dc)max and the fi rst crossing of vref(dc). hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih(dc)min and the first crossing of vref(dc). if the actual signal is always later than the nomi nal slewrate line between shaded ?dc to vref (dc) region?, use nominal slew rate for derating value (see figure 15). if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to vref(dc) region?, the slew rate of a tangent line to the actual signal from the dc level to vref(dc) level is used for derating value (see figure 16). although for slow slew rates the total setup time might be negat ive (i.e. a valid input signal will not have reached vih/il(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach vih/il(ac). for slew rates in between the values listed in table 2 the derating values may obtai ned by linear interpolation. these values are typically not subj ect to production test. they are ve rified by design and characterization. ? tis and ? tih derating values for ddr2-667, ddr2-800 ck, ck differential slew rate 2.0 v/ns 1.5 v/ns 1.0 v/ns units notes ? tis ? tih ? tis ? tih ? tis ? tih command/ address slew rate(v/ns) 4.0 +150 +94 +180 +124 +210 +154 ps 1 3.5 +143 +89 +173 +119 +203 +149 ps 1 3.0 +133 +83 +163 +113 +193 +143 ps 1 2.5 +120 +75 +150 +105 +180 +135 ps 1 2.0 +100 +45 +130 +75 +160 +105 ps 1 1.5 +67 +21 +97 +51 +127 +81 ps 1 1.0 0 0 +30 +30 +60 +60 ps 1 0.9 -5 -14 +25 +16 +55 +46 ps 1 0.8 -13 -31 +17 -1 +47 +29 ps 1 0.7 -22 -54 +8 -24 +38 +6 ps 1 0.6 -34 -83 -4 -53 +26 -23 ps 1 0.5 -60 -125 -30 -95 0 -65 ps 1 0.4 -100 -188 -70 -158 -40 -128 ps 1 0.3 -168 -292 -138 -262 -108 -232 ps 1 0.25 -200 -375 -170 -345 -140 -315 ps 1 0.2 -325 -500 -295 -470 -265 -440 ps 1 0.15 -517 -708 -487 -678 -457 -648 ps 1 0.1 -1000 -1125 -970 -1095 -940 -1065 ps 1
rev. 1.0 august 2009 k4t51163qi 33 of 42 industrial ddr2 sdram v ss setup slew rate setup slew rate rising signal falling signal ? tf ? tr v ref(dc) - vil(ac)max ? tf = vih(ac)min - v ref(dc) ? tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate vref to ac region vref to ac region figure 13 - illustration of nominal slew rate for tis ck ck tis tih tis tih
rev. 1.0 august 2009 k4t51163qi 34 of 42 industrial ddr2 sdram v ss setup slew rate setup slew rate rising signal falling signal ? tf ? tr tangent line[v ref(dc) - vil(ac)max] ? tf = tangent line[vih(ac)min - v ref(dc) ] ? tr = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line figure 14 - illustration of tangent line for tis ck ck tis tih tis tih
rev. 1.0 august 2009 k4t51163qi 35 of 42 industrial ddr2 sdram v ss hold slew rate hold slew rate falling signal rising signal ? tr ? tf v ref(dc) - vil(dc)max ? tr = vih(dc)min - v ref(dc) ? tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max nominal slew rate nominal slew rate dc to v ref region dc to v ref region figure 15 - illustration of nominal slew rate for tih ck ck tis tih tis tih
rev. 1.0 august 2009 k4t51163qi 36 of 42 industrial ddr2 sdram v ss hold slew rate ? tf ? tr tangent line [ vih(dc)min - v ref(dc) ] ? tf = v ddq v ih(ac) min v ih(dc) min v ref(dc) v il(dc) max v il(ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref(dc) - vil(dc)max ] ? tr = rising signal figure 16 - illustration of tangent line for tih ck ck tis tih tis tih
rev. 1.0 august 2009 k4t51163qi 37 of 42 industrial ddr2 sdram 10. the maximum limit for this parameter is not a device limit. the device will operate with a greate r value for this parameter, b ut system performance (bus turnaround) will degrade accordingly. 11. min ( tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i .e. this value can be greater than the minimum specification limits for tcl and tch). for example, tcl and tch are = 50% of the period, less the half period jitter ( tjit(hp)) of the clock source, and less the half period jitter due to crosstalk ( tjit(crosstalk )) into the clock traces. 12. tqh = thp - tqhs, where : thp = minimum half clock period for any given cycle and is de fined by clock high or clock low (tch, tcl). tqhs accounts for: 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one transition followed by t he worst case pull-in of dq on the next transition, both of wh ich are, separately, due to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 13. tdqsq: consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate mismatch between dqs/ dqs and associated dq in any given cycle. 14. tdal = wr + ru{ trp[ns] / tck[ns] }, where ru stands for round up. wr refers to the twr parameter stored in the mrs. for trp, if the result of the division is not already an integer, round up to the next highest integer. tck refers to the application clock period. example: for ddr667 at tck = 3ns with wr programmed to 5 clocks. tdal = 5 + (15 ns / 3 ns) clocks = 5 + (5) clocks = 10 clocks. 15. the clock frequency is allowed to change during se lf refresh mode or precharge power-down mode. 16. odt turn on time min is when the device leav es high impedance and odt resistance begins to turn on. odt turn on time max is whe n the odt resis- tance is fully on. both are measured from taond, which is inte rpreted differently per speed bin. for ddr2-667/800, taond is 2 c lock cycles after the clock edge that registered a first odt hi gh counting the actual input clock edges. 17. odt turn off time min is when the device starts to turn off od t resistance. odt turn off time max is when the bus is in high i mpedance. both are mea- sured from taofd, which is interpreted differently per speed bin. for ddr2-667/800, if tck(avg) = 3 ns is assumed, taofd is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first odt low and by counting the actual in put clock edges. 18. thz and tlz transitions occur in the same access time as vali d data transitions. these parameters are referenced to a specific voltage level which specifies when the device output is no longer driving (thz), or begins driving (tlz ) . figure 17 shows a method to calculate th e point when device is no longer driving (thz), or beginsdriving (t lz) by measuring the signal at two differ ent voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. tlz( dq) refers to tlz of the dqs and tlz(dqs) refers to tlz of the (u/l/r)dqs and (u/l/r )dqs each treated as single-ended signal. 19. trpst end point and trpre begin point are not referenced to a s pecific voltage level but specify when the device output is no l onger driving (trpst), or begins driving (trpre). figure 17 shows a method to calculate these points when the device is no longer driving (trpst), or begins driving (trpre) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consiste nt. figure 17 - method for calculating transitions and endpoints thz trpst end point t1 t2 v oh + x mv v oh + 2x mv v ol + 2x mv v ol + x mv tlz trpre begin point t2 t1 v tt + 2x mv v tt + x mv v tt - x mv v tt - 2x mv tlz,trpre begin point = 2*t1-t2 thz,trpst end point = 2*t1-t2
rev. 1.0 august 2009 k4t51163qi 38 of 42 industrial ddr2 sdram 20. input waveform timing tds with differential data strobe enabled mr[bit10] =0, is referenced from the input signal crossing at t he v ih (ac) level to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the v il (ac) level to the differential data stro be crosspoint for a falling signal applied to the device under test. dqs, dqs signals must be monotonic between v il (dc)max and v ih (dc)min. see figure 18. 21. input waveform timing tdh with differential da ta strobe enabled mr[bit10]=0, is referenced from the differential data strobe cr osspoint to the input signal crossing at the v ih (dc) level for a falling signal and from the differential data strobe crosspoint to the input signal crossing at the v il (dc) level for a rising signal applied to the device under test. dqs, dqs signals must be monotonic between v il (dc)max and v ih (dc)min. see figure 18. 22. input waveform timing is referenced fr om the input signal crossing at the v ih (ac) level for a rising signal and v il (ac) for a falling signal applied to the device under test. see figure 19. 23. input waveform timing is referenced fr om the input signal crossing at the v il (dc) level for a rising signal and v ih (dc) for a falling signal applied to the device under test. see figure 19. tds v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max v ss dqs dqs tdh tds tdh figure 18 - differential input waveform timing - tds and tdh tis ck ck tih tis tih figure 19 - differential input waveform timing - tis and tih v ddq v ih (ac)min v ih (dc)min v ref (dc) v il (dc)max v il (ac)max v ss
rev. 1.0 august 2009 k4t51163qi 39 of 42 industrial ddr2 sdram 24. twtr is at lease two clocks (2 x tc k or 2 x nck) independent of operation frequency. 25. input waveform timing with single-ended data strobe enabled mr[bit 10] = 1, is referenced from the input signal crossing at the vih(ac) level to the sin- gle-ended data strobe crossing vih/l(dc) at the start of its trans ition for a rising signal, and from the input signal crossing at the vil(ac) level to the single-ended data strobe crossing vih/l(dc) at the start of its transition for a falling signal ap plied to the device under tes t. the dqs signal must be monotonic between vil(dc)max and vih(dc)min. 26. input waveform timing with single-ended data strobe enabled mr[bit 10] = 1, is referenced from the input signal crossing at the vih(dc) level to the sin- gle-ended data strobe crossing vih/l(ac) at the end of its transit ion for a rising signal, and from the input signal crossing a t the vil(dc) level to the sin- gle-ended data strobe crossing vih/l(ac) at the end of its transi tion for a falling signal appli ed to the device under test. th e dqs signal must be monotonic between vil(dc)max and vih(dc)min. 27. tckemin of 3 clocks means cke must be registered on three cons ecutive positive clock edges. cke must remain at the valid input level the entire time it takes to achieve the 3 clocks of registration. thus, after any cke trans ition, cke may not transition from its valid le vel during the time period of tis + 2 x tck + tih. 28. if tds or tdh is violated, data corruption may occur and the data must be re-written with valid data before a valid read can b e executed. 29. these parameters are measured from a command/address signal (cke, cs , ras , cas , we , odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck ) crossing. the spec values are not affect ed by the amount of clock jitter applied (i.e . tjit(per), tjit(cc), etc.), as the set up and hold are relative to the clock signal cros sing that latches the command/address. that is, these parameters should be met whethe r clock jitter is present or not. 30. these parameters are measured from a data strobe signal ((l/u/r)dqs/dqs ) crossing to its respec tive clock signal (ck/ck ) crossing. the spec val- ues are not affected by the amount of clock jitter applied (i.e. tj it(per), tjit(cc), etc.), as th ese are relative to the clock signal crossing. that is, these parameters should be met whether clock jitter is present or not. 31. these parameters are measured from a data signal ((l/u)dm, (l/u)d q0, (l/u)dq1, etc.) transition edge to its respective data str obe signal ((l/u/ r)dqs/dqs ) crossing. 32. for these parameters, the ddr2 sdram device is characterized and verified to support tn param = ru{tparam / tck(avg)}, which is in clock cycles, assuming all inpu t clock jitter specific ations are satisfied. for example, the device will support tnrp = ru{trp / tck(avg)}, wh ich is in clock cycl es, if all input cloc k jitter specificati ons are met. this means: for ddr2-667 5-5-5, of which trp = 15ns, the device will support tnrp = ru{trp / tck(avg)} = 5, i.e. as long as the input clock jitter specifications are met, precharge command at tm and active command at tm+5 is va lid even if (tm+5 - tm) is less than 15ns due to input clock j itter. 33. tdal [nck] = wr [nck] + tnrp [nck] = wr + ru {trp [ps] / tck(av g) [ps] }, where wr is the value programmed in the mode registe r set. 34. new units, ?tck(avg)? and ?nck?, are introduced in ddr2-667 and ddr2- 800. unit ?tck(avg)? represents the actual tck(avg) of the input clock under operation. unit ?nck? represents one clock cycle of the input clock, counti ng the actual clock edges. note that in ddr2-400 and ddr2-533, ?tck? is used for both concepts. ex) txp = 2 [nck] means; if power down exit is registered at tm, an active command may be registered at tm+2, even if (tm+2 - t m) is 2 x tck(avg) + terr(2per),min. 35. input clock jitter spec parameter. these parameters and the ones in the table below are referred to as 'input clock jitter spe c parameters' and these parameters apply to ddr2-667 and ddr2-800 only. the jitter spec ified is a random jitter meet ing a gaussian distribution. parameter symbol ddr2-667 ddr2-800 units notes min max min max clock period jitter tjit(per) -125 125 -100 100 ps 35 clock period jitter during dll locking period tjit(per,lck) -100 100 -80 80 ps 35 cycle to cycle clock period ji tter tjit(cc) -250 250 -200 200 ps 35 cycle to cycle clock period jitter during dll locking period tjit(cc,lck) -200 200 -160 160 ps 35 cumulative error across 2 cycles terr(2per) -175 175 -150 150 ps 35 cumulative error across 3 cycles terr(3per) -225 225 -175 175 ps 35 cumulative error across 4 cycles terr(4per) -250 250 -200 200 ps 35 cumulative error across 5 cycles terr(5per) -250 250 -200 200 ps 35 cumulative error across n cycles, n = 6 ... 10, inclusive terr(6-10per) -350 350 -300 300 ps 35 cumulative error across n cyc les, n = 11 ... 50, inclusive terr(11-50per) -450 450 -450 450 ps 35 duty cycle jitter tjit(duty) -125 125 -100 100 ps 35
rev. 1.0 august 2009 k4t51163qi 40 of 42 industrial ddr2 sdram definitions : - tck(avg) tck(avg) is calculated as the average clock period across any consecutive 200 cycle window. - tch(avg) and tcl(avg) tch(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. tcl(avg) is defined as the aver age low pulse width, as calculated across any consecutive 200 low pulses. - tjit(duty) tjit(duty) is defined as the cumulative set of tch jitter and tcl jitter. tch jitter is the largest deviation of any single t ch from tch(avg). tcl jitter is the largest deviation of any single tcl from tcl(avg). tjit(duty) = min/max of {tjit(ch), tjit(cl)} where, tjit(ch) = {tchi- tch(avg) where i=1 to 200} tjit(cl) = {tcli- tcl(avg) where i=1 to 200} - tjit(per), tjit(per,lck) tjit(per) is defined as the largest deviation of any single tck from tck(avg). tjit(per) = min/max of {tcki- tck(avg) where i=1 to 200} tjit(per) defines the single perio d jitter when the dll is already locked. tjit(per,lck) uses the same definition for single period jitter, during the dll locking period only. tjit(per) and tjit(per,lck) are not g uaranteed through final production testing. - tjit(cc), tjit(cc,lck) tjit(cc) is defined as the differenc e in clock period between two consecutiv e clock cycles : tjit(cc) = max of |tck i+1 - tcki| tjit(cc) defines the c ycle to cycle jitter when the dll is already locked. tjit(cc,lck) uses the same definition for cycle to cycle jitter, during the dll locking period only. tjit(cc) and tjit(cc,lck) are not guaranteed through final production testing. - terr(2per), terr (3per), terr (4per), terr (5per), terr (6-10per) and terr (11-50per) terr is defined as the cumulative error across multiple consecutive cycles from tck(avg). terr(nper) = where n = 2 i + n - 1 tck j j = 1 - n x tck(avg) for terr(2per) n = 3 for terr(3per) n = 4 for terr(4per) n = 5 for terr(5per) 6 n 10 for terr(6-10per) 11 n 50 for terr(11-50per) tck(avg) = where n = 200 n tck j j = 1 /n tch(avg) = where n = 200 n tch j j = 1 /(n x tck(avg)) tcl(avg) = where n = 200 n tcl j j = 1 /(n x tck(avg))
rev. 1.0 august 2009 k4t51163qi 41 of 42 industrial ddr2 sdram 36. these parameters are specified per their average values, however it is understood that the following relationship between the a verage timing and the absolute instantaneous timing holds at all times. (min and max of spec values are to be used for ca lculations in the table belo w.) example: for ddr2-667, tch(abs),min = ( 0.48 x 3000 ps ) - 125 ps = 1315 ps 37. thp is the minimum of the absolute half period of the actual input clock. thp is an input parameter but not an input specificat ion parameter. it is used in conjunction with tqhs to derive the dra m output timing tqh. the value to be used fo r tqh calculation is determined by the fo llowing equation; thp = min ( tch(abs), tcl(abs) ), where, tch(abs) is the minimum of the ac tual instantaneous clock high time; tcl(abs) is the minimum of the ac tual instantaneous clock low time; 38. tqhs accounts for: 1) the pulse duration distortion of on-chip clock circuits , which represents how well the ac tual thp at the input is trans ferred to the output; and 2) the worst case push-out of dqs on one transition followed by the worst case pull-in of dq on the next transition, both of which are independent of each other, due to data pin skew, output pattern effects, and p-channel to n-channel variation of the output drivers 39. tqh = thp - tqhs, where: thp is the minimum of the absolute half period of the actual i nput clock; and tqhs is the specification value under the max col umn. {the less half-pulse width distortion present, the larger t he tqh value is; and the larger the valid data eye will be.} examples: 1) if the system provides thp of 1315 ps into a ddr2- 667 sdram, the dram provides tqh of 975 ps minimum. 2) if the system provides thp of 1420 ps into a ddr2- 667 sdram, the dram provides tqh of 1080 ps minimum. 40. when the device is operated with input clock jitter, this para meter needs to be derated by the actual terr(6-10per) of the inpu t clock. (output derat- ings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-667 sdram has terr(6-10per),min = - 272 ps and terr(6-10per),max = + 293 ps, th en tdqsck,min(derated) = tdqsck,min - terr(6-10per),max = - 400 ps - 293 ps = - 693 ps and tdqsck,max(derated) = tdqsck,max - terr (6- 10per),min = 400 ps + 272 ps = + 672 ps. similarly, tlz(dq) for ddr2-667 derates to tlz(dq),min(derated) = - 900 ps - 293 ps = - 1193 ps and tlz(dq),max(derated) = 450 ps + 272 ps = + 722 ps. 41. when the device is operated with input cloc k jitter, this parameter needs to be derated by the actual tjit(per) of the input c lock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-667 sdram has tjit(per),min = - 72 ps and tjit(per),max = + 93 ps, then trpre,m in(derated) = trpre,min + tjit(per),min = 0.9 x tck(avg) - 72 ps = + 2178 ps and trpre,max(derated) = trpre,max + tjit(per),max = 1.1 x tck(a vg) + 93 ps = + 2843 ps. 42. when the device is operated with input clock jitter, this para meter needs to be derated by the actual tjit(duty) of the input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-667 sdram has tj it(duty),min = - 72 ps and tjit(duty),max = + 93 ps, then trpst ,min(derated) = trpst,min + tjit(duty),min = 0.4 x tck(avg) - 72 ps = + 928 ps and trpst,max(derated) = trpst,max + tjit(duty),max = 0.6 x tck( avg) + 93 ps = + 1592 ps. 43. when the device is operated with input clock jitter, this pa rameter needs to be derated by { - tjit(duty),max - terr(6-10per), max } and { - tjit(duty),min - terr(6-10per),min } of the actual input clock. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr2-667 sdram has terr(6-10per),min = - 272 ps, terr(6- 10per),max = + 293 ps, tjit (duty),min = - 106 ps and tjit(duty),max = + 94 ps, then taof,min(derated) = taof,min + { - tjit(duty),max - terr(6-10per),max } = - 450 ps + { - 94 ps - 293 ps} = - 837 ps and taof,max(derated) = taof,max + { - tjit(duty),min - terr(6-10per),min } = 1050 ps + { 106 ps + 272 ps } = + 1428 p s. parameter symbol min max units absolute clock period tck(abs) tck(avg),min + tjit(per),min tck(avg),max + tjit(per),max ps absolute clock high pulse width tch(abs) tch(avg),min x tck(avg),min + tjit(duty),min tch(avg),max x tck(avg),max + tjit(duty),max ps absolute clock low pulse width tcl(abs) tcl(avg),min x tck(avg),min + tjit(duty),min tcl(avg),max x tck(avg),max + tjit(duty),max ps
rev. 1.0 august 2009 k4t51163qi 42 of 42 industrial ddr2 sdram 44. for taofd of ddr2-667/800, the 1/2 clock of nck in the 2.5 x nck assumes a tch(avg), average input clock high pulse width of 0 .5 relative to tck(avg). taof,min and taof,max should each be derated by the same amount as the actual amount of tch(avg) offset present at th e dram input with respect to 0.5. for example, if an input clock has a worst case tch(avg) of 0.48, the taof,min should be derated by subtracting 0.02 x tck (avg) from it, whereas if an input clock has a worst case tch(avg) of 0.52, the taof,max should be derated by adding 0.02 x tck(avg) to it. therefore, we ha ve; taof,min(derated) = tac,min - [0.5 - min(0.5, tch(avg),min)] x tck(avg) taof,max(derated) = tac,max + 0.6 + [max(0.5, tch(avg),max) - 0.5] x tck(avg) taof,min(derated) = min(tac,min, tac,mi n - [0.5 - tch(avg),min] x tck(avg)) taof,max(derated) = 0.6 + max(tac,max, tac,max + [tch(avg),max - 0.5] x tck(avg)) where tch(avg),min and tch(avg),max are the minimum and maximum of tch(avg) actually measur ed at the dram input balls. note that these deratings are in addition to the taof derating per input clock jitter, i.e. tjit(duty) and terr(6-10per). however t ac values used in the equations shown above are from the timing parameter table and ar e not derated. thus the final derated values for taof are; taof,min(derated_final) = taof,min(derated) + { - tjit(duty),max - terr(6-10per),max } taof,max(derated_final) = taof,max(derated) + { - tjit(duty),min - terr(6-10per),min }

▲Up To Search▲

Price & Availability of K4T51163QI-HIE70

	To Download K4T51163QI-HIE70 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .